1. Technical Field
The present invention relates to a comparator, a circuit device, a physical quantity sensor, an electronic device, a vehicle, or the like.
2. Related Art
A time-domain type comparator is known which converts an input voltage level into a time (for example, a delay time of a signal edge, a pulse width of a pulse signal, a period of a clock signal, or the like), and performs comparison of the input voltage level by comparison of the time.
For example, U.S. Pat. No. 8,373,444 discloses a time domain-type comparator, and a sequential comparison-type A/D converter using it. The time domain-type comparator of U.S. Pat. No. 8,373,444 includes first and second voltage-time conversion circuits to which first and second input voltages and clock signals are input, and compares the first and second input voltages by comparing delay times (first and second delay times) of the clock signals in the first and second voltage-time conversion circuits. The first voltage-time conversion circuit includes a plurality of delay stages, and each delay stage includes two stages of inverter. An N-type transistor is provided between a first-stage inverter and a ground, and a P-type transistor is provided between a second-stage inverter and a power supply. Then, a first input voltage is input to the N-type transistor, and a second input voltage is input to the P-type transistor. The second voltage-time conversion circuit has the same configuration, but the second input voltage is input to the N-type transistor and the first input voltage is input to the P-type transistor. With such a configuration, the magnitude relation of the first and second delay times are determined according to the magnitude relation of the first and second input voltages, and voltage comparison is possible.
In the time domain-type comparator as described above, the delay time (a gain for converting a voltage into a time) is determined by the number of delay stages, and there is a problem in that a layout area is required by the number of delay stages. For example, in order to increase the delay time, it is necessary to increase the number of delay stages and thus the layout area increases.
For example, since U.S. Pat. No. 8,373,444 is configured such that only one edge of the clock signal is delayed, the number of stages needs to be increased in order to increase the delay time. That is, in a case where one edge (a rising edge) is input to a plurality of delay stages and the edge is delayed, the next input edge is necessarily the other edge (a falling edge). Therefore, even if the outputs of a plurality of delay stages are fed back to the input side to attempt to repeatedly perform delay, the falling edge of the second round cannot be delayed. That is, since it is not possible to feedback the outputs of a plurality of delay stages back to the input side and to repeatedly perform delay, it is necessary to increase the number of stages in order to increase the delay time.